DDTV Complete pdf notes(material 2)

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DDTV Complete pdf notes(material 2)

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Unit-1:

INTRODUCTION TO VERILOG,Verilog as HDL, Levels of design Description, Concurrency, Simulation and Synthesis, FunctionalVerification, System Tasks, Programming Language Interface (PLI), Module, Simulation and SynthesisTools, Test Benches.

Unit-2:

GATE LEVEL MODELING,AND Gate Primitive, Module Structure, Other Gate Primitives, Illustrative Examples, Tri-State Gates,Array of Instances of Primitives, Design of Flip-flops with Gate Primitives, Delays, Strengths and
Contention Resolution, Net Types, Design of Basic Circuits.

Unit-3:

BEHAVIORAL MODELING,Introduction, Operations and Assignments, Functional Bifurcation, Initial Construct, Always Construct,Examples, Assignments with Delays, Wait construct, Multiple Always Blocks, Blocking and Non
blocking Assignments, The case statement, iƒ and iƒ-else constructs, Assign-de-assign construct, repeat
construct, for loop , The disable construct, while loop, forever loop, Parallel blocks, Force-release,
construct, Event.

Unit-4:

SWITCH LEVEL MODELLING,Basic Transistor Switches, Cmos Switch, Bidirectional Gates, Time Delays With Switch Primitives,Instantiations With Strengths And Delays, Strength Contention With Trireg Nets.

Unit-5:

Sequential Models – Feedback Model, Capacitive Model, Implicit Model, Basic Memory, Components,
Functional Register, Static Machine Coding, Sequential Synthesis, Component Test and Verification: Test
bench – Combinational Circuit Testing, Sequential Circuit, Testing, Test bench Techniques, Design
Verification, Assertion Verification.

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