SYLLABUS- INTRODUCTION TO VERILOG: Verilog as HDL, Levels of design Description, Concurrency, Simulation and Synthesis, Functional Verification, System Tasks, Programming Language Interface (PLI), Module, Simulation and Synthesis Tools, Test Benches.
LANGUAGE CONSTRUCTS AND CONVENTIONS: Introduction, Keywords, Identifiers, White Space Characters, Comments, Numbers, Strings, Logic Values, Strengths, Data Types, Scalars and Vectors, Parameters, Operators
SYLLABUS- GATE LEVEL MODELING AND Gate Primitive, Module Structure, Other Gate Primitives, Illustrative Examples, Tri-State Gates, Array of Instances of Primitives, Design of Flip-flops with Gate Primitives, Delays, Strengths and Contention Resolution, Net Types, Design of Basic Circuits.
MODELING AT DATA FLOW LEVEL Introduction, Continuous assignment structures, Delays and continuous, Assignments, Assignment to vectors, Operators
SYLLABUS- Introduction to Verilog, Levels of design description – Circuit level, gate level, data flow, Behavior level, Overall design structure in verilog, Concurrency, Simulation and synthesis, Functional verification, Test inputs for test benches, Constructs for modeling timing delays, System tasks, Programming language interface, Module
Language constructs and convention in verilog- Introduction, Identifiers, White space characters, Numbers – Integer numbers, Real numbers, Strings, Different ways of number representations in verilog, Logic values, Data types, Scalars and vectors, Parameters, Operators
Modeling – Introduction, AND GATE Primitive, Module structure, Other GATE primitive, Tri-state gates, Array of instances of primitives, Observations, Design of Flip flops with gate primitives, Delays, Strength and contention resolution, Contention between net and gate primitive outputs, Net assignments with part connections, Net types, Tri, Modeling at data flow level – introduction, delays and continuous assignments, Assignment to vectors, Operators, Behavioral Modeling – introduction, operation and assignments, Functional bifurcation,
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Frequently Asked Questions
Q1: How to explain verilog as an HDL?
A1: Verilog aimed at providing a functionally tested and a verified design description for the target FPGA or ASIC. The language has a two major functions
Fulfilling the need for a design description and
Fulfilling the need for verifying the design for functionality and timing constraints (propagation delay, critical path delay, slack, setup, and hold times)
Q2: What are the levels of design description?
A2: There are three levels of design description
1. Circuit Level: At the circuit level, a switch is the basic element with which digital circuits are built. At the next higher level of abstraction, switches can be combined to form inverters and other gates. The basic MOS switches built into its constructs are contained by the Verilog. This can be used to build basic circuits like basic logic gates, inverters, simple 1-bit dynamic and static memories
2. Gate Level :- At the next higher level of abstraction, design is carried out in terms of basic gates. All the basic gates are easily available as complete modules. They are called as Primitives. These primitives individually, are defined in terms of its inputs and outputs. Primitives can be included into design descriptions directly.
3. Data Flow :- Data flow is the next higher level of abstraction. All possible operations on signals and variables are represented here in terms of assignments. All logic and algebraic operations are accommodated. Concerned block’s continuous functioning can be defined by the assignments. At the data flow level, signals are assigned through the data manipulating equations. All such assignments are concurrent in nature.